Powerpc 970fx kit and other links

[tinkerer15khz]

http://www-128.ibm.com/developerworks/power/ppc970fx/

"The IBM PowerPC® 970FX Evaluation Kit software includes the IBM PowerPC Initialization Boot Software (PIBS) resident in the flash memory on the board, PIBS source code, the IBM Embedded PowerPC Operating System (EPOS), sample application programs, and application development libraries and tools. Documentation includes board and software technical specifications, evaluation board schematics, and an application note that describes step-by-step instructions on how to obtain and build GNU software development tools for use with the evaluation kit software. Also included is software for the PowerPC 405EP service processor on the board that manages power, initialization, clocks, configuration, and other system tasks. The service processor software also utilizes PIBS and EPOS."

http://www-128.ibm.com/developerworks/power/pa-slof/?S_TACT=105AGX16&S_CMP=HP

"Why

The SLOF source code provides a largely machine-independent BIOS and illustrates what's needed to initialize and boot Linux™, a hypervisor, or any other operating system or virtualization layer on PowerPC-based machines based on the de-facto industry Open Firmware boot standard. This download is made available under a liberal Open Source Software (OSS) license."

[tinkerer15khz]

http://www-128.ibm.com/developerworks/library/pa-powerppl/

" POWER5  ™
Released in 2003: 276 million transistors per processor
Like the POWER3 and POWER4, the POWER5 unifies the POWER and PowerPC architectures. The POWER5 is also based on the 130-nanometer copper/SOI process, and features communications acceleration, chip multiprocessing, a larger L2 cache, a memory controller on the chip, simultaneous multithreading, advanced power management, eFuse (morphing) and hypervisor technology. IBM servers built with the POWER5 feature up to ten LPARs capable of running up to 256 independent operating systems on the higest end. POWER5 processors can be found hanging about in iSeries and pSeries servers, as well as in the first IBM entry-level UNIX/Linux box, the OpenPower™ line. IBM introduced the POWER5+™ processors, which are built with a 90-nanometer process similar to that used with the Cell Broadband Engine, in 2005. POWER5+ ups the clockspeed significantly -- on a smaller die."

[tinkerer15khz]

http://www-128.ibm.com/developerworks/power/library/pa-archguidev2/?S_TACT=105AGX16&S_CMP=DWPA

"This three-volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM® POWER5™ processor family. Verson 2.01 describes POWER4™ and POWER4+™ processors."

[tinkerer15khz]

http://www-941.ibm.com/collaboration/wiki/display/LinuxP/POWER5+Hypervisor

"The POWER Hypervisor is a component of the system's firmware that will always be installed and activated, regardless of system configuration. It operates as a hidden partition, with no entitled capacity assigned to it.
Newly architected Hypervisor calls (hcalls) provide a means for the operating system to communicate with the POWER Hypervisor, allowing more efficient usage of physical processor capacity by supporting the scheduling heuristic of minimizing idle time."

http://www-941.ibm.com/collaboration/wiki/download/attachments/677/P5-hypervisor.png

[tinkerer15khz]

http://www-941.ibm.com/collaboration/wiki/display/LinuxP/Boot+Process+on+POWER

"pSeries CHRP systems use a firmware that conforms to the open firmware IEEE Std. 1275-1994. Open Firmware is primarily a boot firmware that does not specify a particular system or processor. It also provides a machine independent devices tree interface that lists the properties of each IO device which can be displayed and altered using a command line interface."

[tinkerer15khz]

http://www.research.ibm.com/journal/rd/494/sinharoy.html

"We enhanced thread-level parallelism by allowing two threads, or instruction streams, to execute on each of the two processor cores. We first present background information on different multithreaded hardware implementations. We then provide a brief overview of the POWER5 structure and contrast it to a POWER4 system. With that as background, we describe the POWER5 simultaneous multithreading (SMT) implementation in detail."