Another glitch chip - X360Glitch, any opinion?

[pudrik]

I tried modifying the cable to only use the 3k3 VCC resistor with no luck. I've now tried to power the board with the strobe pin, which on this new LPT card delivers 4.9V, and now nothing seems to work. I'm back at square one with "TDO stuck at 1", even though I reset everything back to the state where I got 360gcprog half working. Tonight I'm going to build a completely new cable and do it quite a bit shorter this time. The one I'm currently trying is about 60cm. I'll try to make the new one about 10cm or something...
I'm starting to wonder if the CPLD is fried...

PM if you want me to program the chip for you, since you obviously live in sweden.

[pudrik]

I got impact to recognize the chip and program it,but when i readback and compare the files.They are different in size..one is 34kb and the one i read back is 27kb?Is there something im missing?I have not tried it yet on a actual xbox but was curious?

Not sure bit it might be that the readback is raw data of the inside of the CPLD, unlike the JED that contains Chip chain info and programming instructions etc.. but still not sure, ive used 360gc to program most chips easier and doesnt require impact. (same cable)

[nob]

Hello, could somebody tell me how the X360Glitch can be connected? I have a Xilinx-LPT-Cable and I always get the message "not compatible". A Coolrunner II chip works. But at the Coolrunner II chip I added a cable with 3.3V from the DVD cable to the VCC point. Do you have to do something similar with the X360Glitch? Thanks.

[johnscrub]

I got impact to recognize the chip and program it,but when i readback and compare the files.They are different in size..one is 34kb and the one i read back is 27kb?Is there something im missing?I have not tried it yet on a actual xbox but was curious?

Not sure bit it might be that the readback is raw data of the inside of the CPLD, unlike the JED that contains Chip chain info and programming instructions etc.. but still not sure, ive used 360gc to program most chips easier and doesnt require impact. (same cable)

Hey thanks for responding..i was thinking something along that line but wasnt positive.I can never get 360gc to recoognize the chip.even after i got impact to.well im going to try it in an xbox today at some point and see that it works.I also modifed the one i had in my falcon with the wire from i2 to d3 and works great!!boots fast even when cold!!

[johnscrub]

Hello, could somebody tell me how the X360Glitch can be connected? I have a Xilinx-LPT-Cable and I always get the message "not compatible". A Coolrunner II chip works. But at the Coolrunner II chip I added a cable with 3.3V from the DVD cable to the VCC point. Do you have to do something similar with the X360Glitch? Thanks.

Check post 35 in this thread...yes it has to have the 3.3v  power to J2..read that part of the thread first

[pudrik]

I got impact to recognize the chip and program it,but when i readback and compare the files.They are different in size..one is 34kb and the one i read back is 27kb?Is there something im missing?I have not tried it yet on a actual xbox but was curious?

Not sure bit it might be that the readback is raw data of the inside of the CPLD, unlike the JED that contains Chip chain info and programming instructions etc.. but still not sure, ive used 360gc to program most chips easier and doesnt require impact. (same cable)

Hey thanks for responding..i was thinking something along that line but wasnt positive.I can never get 360gc to recoognize the chip.even after i got impact to.well im going to try it in an xbox today at some point and see that it works.I also modifed the one i had in my falcon with the wire from i2 to d3 and works great!!boots fast even when cold!!

UPDATE The wire I2 to D3 seem to be same as closing programming bridge (close to C2)

[Pigbait]

Sorry for the question but I ordered some 360 glitch chips and I revived the Jasper fat model, will the work in a falcon or will I need to reprogram the chip? There site is very vague on chip type only says slim and fat, but on the back of my chip it says Jasper?

[k0mpresd]

you will need to program it for falcon. they sell the 4 different types on volumerates.com. slim, japser, falcon, and zephyr.

[Pigbait]

Thanks

[audioprouk]

I had real problems with the x360 glitch chips , HOWEVER i figured it out . I just could NOT get them to glitch properly . i tried and tried . I`ve had 3 and all were the same . I figured out that you HAVE to bridge just the "slim" point NOT the r3 point as it says in the on site guide . I use them all the time now are they are just fine if you use them as i describe !

[Pigbait]

I had real problems with the x360 glitch chips , HOWEVER i figured it out . I just could NOT get them to glitch properly . i tried and tried . I`ve had 3 and all were the same . I figured out that you HAVE to bridge just the "slim" point NOT the r3 point as it says in the on site guide . I use them all the time now are they are just fine if you use them as i describe !

i can comfirm this works, had a jasper i could not get to boot and now boots in seconds

[wiggim]

I had real problems with the x360 glitch chips , HOWEVER i figured it out . I just could NOT get them to glitch properly . i tried and tried . I`ve had 3 and all were the same . I figured out that you HAVE to bridge just the "slim" point NOT the r3 point as it says in the on site guide . I use them all the time now are they are just fine if you use them as i describe !

3 days to figure this out. Thank You!
I tried bridging BOTH without a go (r3 and slim point). JUST the slim point got a falcon going perfect! just a few seconds and its up and going.

Now to program these - I did it, several times. Verified fine.. I know they won't work without a bridge. but will seem to program fine using R2 or R3 bridge. Is one more correct than the other? Im thinking R2 is to program, C5 is for Phat..

as for slims? did they reverse these points so R3 needs to be bridged? anyone successfully do a slim with them yet?

Here is my redone 'phat' schematic. Unsure about the programming. If anyone wants to chime in on what they did please let me know!


Trying to email the team and see what their response is to the above diagram and slim installs.

[johnscrub]

Thats weird as i have one in a falcon with the r3 bridged and it glitches just fine!I get it to boot up within 5 to 10 secs..

[k0mpresd]

Thats weird as i have one in a falcon with the r3 bridged and it glitches just fine!I get it to boot up within 5 to 10 secs..

me too. except i ended up installing it in a big block jasper. after a few wire length tweaks it glitched like a champ.

[tired]

With R3 bridged I had cold boot problems on falcons. Console would glitch fine for hours, next day from cold boot
, nothing until the console warmed up. Found this thread and moved the bridge point and the cold boot problem was fixed.

Have successfully reporgrammed these using a nand-x. No bridging required. I spliced off the coolrunner cable.

Couldn't get this chip to glitch with any speed on a 16MB jasper, tried the 68NF fix with no improvement. Fitted a coolrunner and had the same problem, added 68NF cap fix and console boots like it's a JTAG. Posting this info for anybody with Jasper problems.

[oveis]

With R3 bridged I had cold boot problems on falcons. Console would glitch fine for hours, next day from cold boot
, nothing until the console warmed up. Found this thread and moved the bridge point and the cold boot problem was fixed.

Have successfully reporgrammed these using a nand-x. No bridging required. I spliced off the coolrunner cable.

Couldn't get this chip to glitch with any speed on a 16MB jasper, tried the 68NF fix with no improvement. Fitted a coolrunner and had the same problem, added 68NF cap fix and console boots like it's a JTAG. Posting this info for anybody with Jasper problems.

are you mean you used 68nf on matrix glitcher with no succes and then you used  tx coolrunner with 68nf and you succeed ?

[pudrik]

With R3 bridged I had cold boot problems on falcons. Console would glitch fine for hours, next day from cold boot
, nothing until the console warmed up. Found this thread and moved the bridge point and the cold boot problem was fixed.

Have successfully reporgrammed these using a nand-x. No bridging required. I spliced off the coolrunner cable.

Couldn't get this chip to glitch with any speed on a 16MB jasper, tried the 68NF fix with no improvement. Fitted a coolrunner and had the same problem, added 68NF cap fix and console boots like it's a JTAG. Posting this info for anybody with Jasper problems.

Had sam problem on jasper 512mb glitch time was about 20 -40 min even had to use multibuilder 0.2 to make it work (seems that it skips a crusial part needed for slim "fcrt" but doesnt seem to matter on fat)

It boots within 5 sec.
Try adding 100nf Capacitor between J4A and GND on chip.
(i think the reason for this is improper debouncing of the Reset signal, CPU doesnt recognice the signal as "VALID level" only noice)

[pudrik]

With R3 bridged I had cold boot problems on falcons. Console would glitch fine for hours, next day from cold boot
, nothing until the console warmed up. Found this thread and moved the bridge point and the cold boot problem was fixed.

Have successfully reporgrammed these using a nand-x. No bridging required. I spliced off the coolrunner cable.

Couldn't get this chip to glitch with any speed on a 16MB jasper, tried the 68NF fix with no improvement. Fitted a coolrunner and had the same problem, added 68NF cap fix and console boots like it's a JTAG. Posting this info for anybody with Jasper problems.

are you mean you used 68nf on matrix glitcher with no succes and then you used  tx coolrunner with 68nf and you succeed ?

I wanna clear up 3 things
1. there is no physical difference between this chip, matrix, tx coolrunner and probably a lot more chips out there, only difference is the PCB the chips are attached to (and possibly some extra components), they use the same firmware and same CPLD.

2. The "WIRE" fix is total bull$#!t, it might work sometimes but it has nothing to do with the LENGTH it has to do with noice induction, a better way of handling this is to have stable debouncing capacitors. (sure if a longer cable works for you then fine feel free to use it, but dont claim that it has something to do with LENGTH, GOD or the EASTER BUNNY)

3. Thickness of your wire doesnt matter in sence "i use AWG32" and "i use AWG28", if you crack the CPLD open youll see tiny tiny wires (almos lite silk threads) connected from the outside pins (huge compared to internal) to the airsuspended logic core within.
Too be blunt Bottleneck effect applies here not the outside wire.
(people claiming otherwise dont know what they are talking about.)

[pudrik]

Dubbel post..

[d4m4n]

I wanna clear up 3 things
1. there is no physical difference between this chip, matrix, tx coolrunner and probably a lot more chips out there, only difference is the PCB the chips are attached to (and possibly some extra components), they use the same firmware and same CPLD.

2. The "WIRE" fix is total bull$#!t, it might work sometimes but it has nothing to do with the LENGTH it has to do with noice induction, a better way of handling this is to have stable debouncing capacitors. (sure if a longer cable works for you then fine feel free to use it, but dont claim that it has something to do with LENGTH, GOD or the EASTER BUNNY)

3. Thickness of your wire doesnt matter in sence "i use AWG32" and "i use AWG28", if you crack the CPLD open youll see tiny tiny wires (almos lite silk threads) connected from the outside pins (huge compared to internal) to the airsuspended logic core within.
Too be blunt Bottleneck effect applies here not the outside wire.
(people claiming otherwise dont know what they are talking about.)

2. It is not bull$#!t. It does add propagation delay. But maybe a proper termination of the transmission line could also help or a very short wire. The needed rise time is very short.

3. Wire length is one part of the equation. The bonding wires are very thin but also very short. It's a matter of resistance where the cross section area and wire length plays a role.