agreed.
cheapest spartan6 costs only 8euro and has LVCMOS15 resolution of 1.23/2.07ns (p. 26, table 28).
it will need 4layer+ pcb though.

why not like this? http://pastebin.com/dNaenbLS
wouldnt case statement generate more complex code than simple logic select?

falcons always work from first try even on homemade etched pcbs.

thats weird that they use PIC based flasher on new board.

squirt360 sold their original idea to these guys? I remember, squirt tried to make actel glitcher and something went wrong.

theres no reason to port slim cb_a to phat, due to that dual cb is possible on phat and actually used in refurb. consoles and rumors saying that guys from rgloader already working on it.

tried to build retail nand with your own filesystem? Theres same issue with extended.bin used for IPTV apps based on MS Mediaroom. you need to use FS from your console, not public packages.

read this thread http://www.xboxhacker.org/index.php?topic=17535.0
and use search.

omg, dont use MG PADS for this, PADS is huge EDA system for complex designs. It costs tons of money, forget about it.
use CadSoft EAGLE Light, because it is free, simple to use and popular. look at other projects like x360 spi flasher - they are done in EAGLE.

I've used itead for 100 mm x 50 mm boards, but when you laying out board for cheap PCB manufacturers like them - be aware that they usually cant do 6/6/6 mil tech. process good.
For iTead you can checkout this document https://github.com/dren-dk/HAL900/wiki/Quirks-of-PCB-manufacturing-at-ITead

about delivery and times - iTead usually does PCBs in 3 days and then you just wait for delivery from China, if youre in US - using local PCB manufacturer will be better.

iTeadStudio OpenPCB prototyping service - http://iteadstudio.com/store/index.php?main_page=index&cPath=19_20&sort=20a&page=1
SeeedStudio Fusion prototyping service - http://www.seeedstudio.com/depot/fusion-pcb-service-p-835.html?cPath=185
SeeedStudio Propagate service (prototyping & assembling) - http://www.seeedstudio.com/propagate/

yep, I understand that, I was talking about what they actually did right now for trinity.

yes, but synch will be affected by wire lenght, and if you remember, needed time window for glitch is pretty small, so even small desynch by that delay can possibly make all glitching proccess fail. so theres two solutions: use same setup everytime OR make dynamic synchronization, which I dont realize on such small CPLD as xc2c64a.

another bad thing about ext. osc:

what is possibilites that they invented another source of wiring problems if they trying to sycnhronize onboard osc with console clocks?
otherwise, what is reference point? will it make kids go nuts with 50cm wires again?

when we use stby_clk we clock our cpld with (console stanby clock + wire_lenght_delay).
when we use external osc to clock cpld we must synchronize osc with console clocks, other we will have jitter and wrong timings. am I right?

nirbeltran,
could you please post a hi res pic of matrix v2?
I'm interested what they did there and what is the name of chip in SSOP package, in other topic we've decided that it is a pl2303 USB-Serial.

you need to setup a pin (real pin on your chip) to port (vhdl) association, in Xilinx ISE this stuff is called constraints and it is in .ucf file.
this file(s) can be generated by FloorPlan from ISE WebPack or you can just write it manually. also this file says what voltage level should pin recieve and transmit.

try to find same (by function, not by name, ofcourse) stuff in Actel's IDE, also, you need to check your chip for compatibility with two voltage levels: 3.3v and 1.8v, if Actel doesnt support those levels - you will need to build a level converter for each incompatibile line, which is not a good way, but it can be solved by external bi-directional level converters like Texas Intruments and NXP sell.

good luck with porting!

if you are familiar with soldering iron and development software - you can port glitch code to any CPLD that supports working with two woltages (3.3, 1.8 ), has enough timing characteristics (7 ns), and are fast enough to do 48MHz for fat and 96MHz for slim.

that is srsly good work Blackaddr! thanks for sharing this.

you used a post reader to detect whats happening with the system or the scope on some testpoint?

about wire lenght - yep, it is a simple delay line. also, check out any DDR memory routing, its all made up with tracks of different lenght to sync everything up. to achieve that, tracks go like this http://wiki.altium.com/download/attachments/5276183/Adding_tuning_lengths.png?version=1&modificationDate=1226546861240

that is just tiny delay lines, for our hack we use same technology, but in different scale.

yep, it isnt for slim, and I dont have a slim to test it out.
also slim hack is much larger and with variable timer it definetly will not fit in 64 macrocells

Jed file is compiled cpld firmware, you cant change it, but, you can fork sources of firmware from GliGli's github and change reset pulse timing. You will need to reflash each time you change timiing.

I've tried to change firmware so you will have two buttons for incrementing and decrementing reset value, everything is here https://github.com/rzk/tools/commit/8db3675c709efa22d37d41db343ac40515364a4e
It works in ISim simulator.

That code is kinda ugly because I'm total n00b in VHDL and it does not fit in xc2c64a CPLD yet, which everybody use for glitchers. I've tried to optimize or remove some things, but it didnt change situation really. I will work on this more and upload changes to my github.

CB is fuse dependent, and when you have 6752, 2 on end means that 2 burnt fuses for this cb is needed. donor CB will not work, because it will fail fuses check and go E80.

also, that means that even if you have good CB on phat, your console still can be upgraded to be not-glichable by MS, because CB is updateable, and nothing stops MS from doing that.